1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a memory core circuit, a memory, and a memory system including the same.
2. Description of the Related Art
As the degree of integration of a memory increases, a space between word lines included in the memory, such as DRAM is reduced. As the space between the word lines is reduced, a coupling effect between adjacent word lines increases.
Meanwhile, whenever data is inputted or outputted to or from a memory cell, a word line toggles between an activated state and a deactivated state. In this regard, as the coupling effect between adjacent word lines increases as described above, the data of a memory cell connected to a word line adjacent to a frequently activated word line may be degraded. Such a phenomenon is called word line disturbance or row hammer. Due to the word line disturbance, the data of a memory cell may be degraded within a retention time of the memory cell to be refreshed.
FIG. 1 is a diagram illustrating a part of a cell array included in DRAM for explaining the word line disturbance.
In FIG. 1, ‘WLL’ corresponds to a frequently activated word line (i.e., a word line having the large number of activations), and ‘WLL−1’ and ‘WLL+1’ correspond to adjacent word lines, which are disposed adjacent to the frequently activated WLL. Furthermore, ‘CL’ denotes a memory cell connected to the frequently activated word line WLL, ‘CL−1’ denotes a memory cell connected to the adjacent word line WLL−1, and ‘CL+1’ denotes a memory cell connected to the adjacent word line WLL+1. The memory cells CL, CL−1 and CL+1 include cell transistors TL, TL−1 and TL+1, respectively, and also include cell capacitors CAPL, CAPL−1 and CAPL+1 respectively.
When the word line WLL is activated or deactivated, the voltages of the word lines WLL−1 and ‘WLL+1’ are increased or decreased due to a coupling effect occurring among the word lines WLL and WLL−1 and among the word lines WLL and WLL+1. Accordingly, the amounts of charges charged in the cell capacitors CAPL−1 and CAPL+1 is affected, so that the data of the memory cells ‘CL−1’ and the ‘CL+1’ may be degraded.
Furthermore, as electromagnetic waves, which are generated while the word line toggles between the activated state and the deactivated state, introduce or discharge electrons into or from the cell capacitors of the memory cells connected to adjacent word lines, data are likely to be degraded.
To prevent degradation of data due to the word line disturbance, it may be necessary to provide a scheme for detecting the frequently activated word lines by counting the number of activations of respective word lines and a scheme for storing the count information. In the case where the scheme for detecting frequently activated word lines is introduced in a memory core circuit, a fail related to the count information may occur.